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74ALVC16722 Low Voltage 22-Bit Register with 3.6V Tolerant Inputs and Outputs
December 2001 Revised December 2001
74ALVC16722 Low Voltage 22-Bit Register with 3.6V Tolerant Inputs and Outputs
General Description
The ALVC16722 low voltage 22-bit register contains twenty-two non-inverting D-type flip-flops with 3-STATE outputs and is intended for bus oriented applications. The design has been optimized for use with JEDEC compliant 200 pin DIMM modules. The 74ALVC16722 is designed for low voltage (1.65V to 3.6V) VCC applications with I/O capability up to 3.6V. The 74ALVC16722 is fabricated with an advanced CMOS technology to achieve high speed operation while maintaining low CMOS power dissipation.
Features
s 1.65V to 3.6V VCC supply operation s 3.6V tolerant inputs and outputs s tPD (CLK to O n) 4.1ns max for 3.0V to 3.6V VCC 5.1ns max for 2.3V to 2.7V VCC 9.2ns max for 1.65V to 1.95V VCC s Power-off high impedance inputs and outputs s Supports live insertion/withdrawal (Note 1) s Meets JEDEC registered module specifications s Latchup conforms to JEDEC JED78 s ESD performance: Human body model > 2000V Machine model >200V
Note 1: To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pull-up resistor; the minimum value of the resistor is determined by the current sourcing capability of the driver.
Ordering Code:
Order Number 74ALVC16722MTD Package Number MTD64 Package Description 64-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter "X" to the ordering code.
(c) 2001 Fairchild Semiconductor Corporation
DS500715
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74ALVC16722
Connection Diagram
Pin Descriptions
Pin Names OE CE CLK D0- D21 O0 - O21 Description Output Enable Input (Active LOW) Clock Enable Input (Active Low) Clock Input Data Inputs 3-STATE Outputs
Truth Table
CLK X X CE X H L L L OE H L L L L Dn X X L H X On Z On L H On

L or H
H = Logic HIGH L = Logic LOW X = Don't Care, but not floating Z = High Impedance On = Previous On before LOW-to-HIGH Clock Transition = LOW-to-HIGH Clock Transition
Functional Description
The ALVC16722 contains twenty-two D-type flip-flops with 3-STATE standard outputs. The twenty-two flip-flops will store the state of their individual D-type inputs that meet the setup and hold time requirements on the LOW-HIGH Clock (CLK) transition, when the Clock-Enable (CE) is LOW. The 3-STATE standard outputs are controlled by the Output-Enable (OE). When OE is HIGH, the standard outputs are in high impedance mode but this does not interfere with entering new data into the flip-flops.
Logic Diagram
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74ALVC16722
Absolute Maximum Ratings(Note 2)
Supply Voltage (VCC) DC Input Voltage (VI) Output Voltage (VO) (Note 3) DC Input Diode Current (IIK) VI < 0V DC Output Diode Current (IOK) VO < 0V DC Output Source/Sink Current (IOH/IOL) DC VCC or GND Current per Supply Pin (ICC or GND) Storage Temperature Range (TSTG)
-0.5V to +4.6V -0.5V to 4.6V -0.5V to VCC +0.5V -50 mA -50 mA 50 mA 100 mA -65C to +150C
Recommended Operating Conditions (Note 4)
Power Supply Operating Input Voltage (VI) Output Voltage (VO) Free Air Operating Temperature (TA) Minimum Input Edge Rate (t/V) VIN = 0.8V to 2.0V, VCC = 3.0V 10 ns/V
Note 2: The Absolute Maximum Ratings are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The parametric values defined in the Electrical Characteristics tables are not guaranteed at the Absolute Maximum Ratings. The "Recommended Operating Conditions" table will define the conditions for actual device operation. Note 3: IO Absolute Maximum Rating must be observed. Note 4: Floating or unused inputs must be held HIGH or LOW.
1.65V to 3.6V 0V to VCC 0V to VCC
-40C to +85C
DC Electrical Characteristics
Symbol VIH Parameter HIGH Level Input Voltage Conditions VCC (V) 1.65 -1.95 2.3 - 2.7 2.7 - 3.6 VIL LOW Level Input Voltage 1.65 -1.95 2.3 - 2.7 2.7 - 3.6 VOH HIGH Level Output Voltage IOH = -100 A IOH = -4 mA IOH = -6 mA IOH = -12 mA 1.65 - 3.6 1.65 2.3 2.3 2.7 3.0 IOH = -24 mA VOL LOW Level Output Voltage IOL = 100 A IOL = 4 mA IOL = 6 mA IOL = 12mA IOL = 24 mA II IOZ ICC ICC Input Leakage Current 3-STATE Output Leakage Quiescent Supply Current Increase in ICC per Input 0 VI 3.6V 0 VO 3.6V VI = V CC or GND, IO = 0 VIH = VCC - 0.6V 3.0 1.65 - 3.6 1.65 2.3 2.3 2.7 3 3.6 3.6 3.6 3 -3.6 VCC - 0.2 1.2 2 1.7 2.2 2.4 2 0.2 0.45 0.4 0.7 0.4 0.55 5.0 10 40 750 A A A A V V Min 0.65 x VCC 1.7 2.0 0.35 x VCC 0.7 0.8 V V Max Units
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74ALVC16722
AC Electrical Characteristics
T A = -40C to +85C, RL = 500 Symbol Parameter CL = 50 pF V CC = 3.3V 0.3V Min fMAX tPHL, tPLH tPZL, tPZH tPLZ, tPHZ tW tS tH Maximum Clock Frequency Propagation Delay CLK to Bus Output Enable Time Output Disable Time Pulse Width Setup Time Hold Time 250 1.3 1.1 1.1 1.5 2.0 0.0 4.1 4.0 3.7 Max V CC = 2.7V Min 200 2.0 1.3 1.3 1.5 2.0 0.0 5.1 5.0 4.7 Max CL = 30 pF V CC = 2.5V 0.2V Min 200 1.5 0.8 0.8 1.5 2.0 0.0 4.6 4.5 4.2 Max V CC = 1.8V 0.15V Min 100 2.0 1.5 1.5 4.0 3.0 0.5 9.2 9.0 7.6 Max ns ns ns ns ns ns ns Units
Capacitance
Symbol CIN COUT CPD Input Capacitance Output Capacitance Power Dissipation Capacitance Parameter VI = 0V or VCC VI = 0V or VCC Outputs Enabled f = 10 MHz, CL = 50 pF Conditions TA = +25C VCC 3.3 3.3 3.3 2.5 Typical 3.5 5.5 13 13 Units pF pF pF
IOUT - VOUT Characteristics
IOH versus VOH IOL versus VOL
FIGURE 1. Characteristics for Output - Pull Up Driver
FIGURE 2. Characteristics for Output - Pull Down Driver
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74ALVC16722
AC Loading and Waveforms
TABLE 1. Values for Figure 1 TEST tPLH, tPHL tPZL, tPLZ tPZH, tPHZ SWITCH Open VL GND
FIGURE 3. AC Test Circuit TABLE 2. Variable Matrix (Input Characteristics: f = 1MHz; tr = tf = 2ns; Z0 = 50 Symbol Vmi Vmo VX VY VL VCC 3.3V 0.3V 1.5V 1.5V VOL + 0.3V VOH - 0.3V 6V 2.7V 1.5V 1.5V VOL + 0.3V VOH - 0.3V 6V 2.5V 0.2V VCC /2 VCC /2 VOL + 0.15V VOH - 0.15V VCC*2 1.8V 0.15V VCC /2 VCC /2 VOL + 0.15V VOH - 0.15V VCC*2
FIGURE 4. Waveform for Inverting and Non-inverting Functions tr = tf 2.0ns, 10% to 90%
FIGURE 5. 3-STATE Output High Enable and Disable Times for Low Voltage Logic tr = tf 2.0ns, 10% to 90%
FIGURE 6. 3-STATE Output Low Enable and Disable Times for Low Voltage Logic tr = tf 2.0ns, 10% to 90%
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74ALVC16722 Low Voltage 22-Bit Register with 3.6V Tolerant Inputs and Outputs
Physical Dimensions inches (millimeters) unless otherwise noted
64-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide Package Number MTD64 Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. www.fairchildsemi.com 6 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com

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